In a multilayer wiring board such as a printing wiring board or an interposer substrate, in order to decrease an alternating-current impedance with respect to a ground of a power supply line or to filter a noise component so as not to be transmitted to the subsequent circuit, a surface mount chip capacitor is mounted as a decoupling capacitor (bypass capacitor).
However, in recent years, according to a decrease in a power supply voltage of an active circuit and an increase in consumption current, a demand for suppression of variation in the power supply voltage has become strong. Thereby, influence due to parasitic resistance or parasitic inductance in a lead wiring from the power supply line to the decoupling capacitor easily occurs, and there is a problem in that the decoupling capacitor mounted on the surface of the printing wiring board does not function.
Therefore, a trend which significantly suppresses parasitic impedance by embedding a decoupling capacitor in the printing wiring board or the interposer substrate as a component has been developed. However, in the embedding of the component, there are problems that the substrate is thicker when the component is embedded, the parasitic inductance remains due to a land which is necessary for mounting the component, and the like.
For example, a method for solving the above-described problems is described in Japanese Patent No. 3816508. Japanese Patent No. 3816508 discloses a technology in which a thin film capacitor having a dielectric layer between an upper electrode and a lower electrode is embedded in a printing wiring board.